Congrats to Islam, Mehmet and ICTEAM, UC Louvain.
AI-Driven Integrated Circuit Design: A Survey of Techniques, Challenges, and Opportunities, IEEE ACCESS
Analog and radio-frequency integrated circuit (RFIC) design has traditionally been defined by its inherent complexity, reliance on manual iterations, and dependence on domain-specific heuristics. Recently, however, this landscape has been undergoing a transformative shift propelled by advancements in Artificial Intelligence (AI) and Machine Learning (ML). This survey provides a systematic and forward-looking review of AI-enabled methodologies—including evolutionary algorithms, Bayesian optimization, reinforcement learning, deep learning, and large language models—as applied to key design and measurement stages: circuit topology and structure synthesis, circuit optimization, layout automation, and post-silicon calibration and fault diagnosis. By mapping these intelligent techniques to each phase of the analog and RFIC development pipeline, we identify emerging trends, persistent challenges such as generalization and data efficiency, and the trajectory toward fully autonomous, scalable, and innovation-driven analog/RFIC design. Beyond circuit design, this evolving ecosystem is also poised to revolutionize the broader Electronic Design Automation (EDA) landscape. This article aims to serve as a comprehensive and authoritative reference for academic researchers and industry practitioners seeking to leverage AI in next-generation circuit and system design.
Congrats to all Consortium Members; Engin, Günhan, Fabio, Rafael, Francisco, Ricardo organizing and chairing the SMACD 2025 conference.
21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design
The 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD 2025) has been held from 7 to 10 July 2025 in Istanbul, Türkiye. SMACD is a premier forum dedicated to the advancement of modeling, simulation, and synthesis techniques for analog, mixed-signal, RF, and multi-domain circuits and systems, as well as emerging technologies such as MEMS, nanoelectronics, and bio-inspired circuits. The conference provides a platform for researchers, engineers, and industry professionals to exchange innovative ideas, present state-of-the-art results, and discuss challenges and applications in circuit design, with a focus on both methodological developments and practical implementation. Attendees can participate in technical sessions, workshops, and tutorials, fostering collaboration and knowledge dissemination across academia and industry.
Congrats to Fábio, and INESC-ID, Lisbon, Portugal
and Instituto Superior Técnico, Universidade de Lisboa, Portugal
On the Usage of Genetic Algorithms, Reinforcement Learning and Bayesian Optimisation for RF IC Design Automation, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2025
The design of Radio Frequency (RF) Integrated Circuits (ICs) is a highly complex and computationally intensive task, requiring precise optimisation of multiple parameters to achieve desired performance. Traditional design methodologies rely heavily on expert knowledge and iterative simulations, leading to prolonged development cycles. In this work, we explore the application of three powerful artificial intelligence (AI)-driven optimisation techniques—Genetic Algorithms (GA), Reinforcement Learning (RL), and Bayesian Optimisation (BO)—to automate and enhance the RF IC design process. We evaluate their effectiveness in optimising key design parameters for a Power Voltage Controlled Oscillator (P-VCO). Due to the difference in the studied techniques, it is not straighforward to compare the performance of these techniques in terms of convergence speed and computational efficiency while achieving significant quality designs. However, the experimental results demonstrated here by all three methods, prove that AI-driven optimisation can significantly reduce design time while achieving superior performance when compared to conventional methods. This work highlights the potential of AI in revolutionising RF IC design automation and paves the way for more efficient and intelligent design methodologies.
Congrats to Engin, and Gebze Technical University
An Open-Source EM Simulation Flow Based on a High-Level Python API, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2025
We present a high-level Python API that enables a fully open-source electromagnetic (EM) and EM-circuit co-simulation flow. The API integrates OpenEMS for 3D full-wave EM simulation, automating critical tasks such as GDSII import, port definitions, meshing, and sequential multi-port excitation to generate the S-parameter matrix. Another key contribution of this work is integration of Xyce for circuit-level characterization, and the implementation of vector fitting techniques to convert multi-port S-parameters into SPICE sub-circuit models, overcoming the limitation of all open-source circuit simulators that only support two-port S-parameter files. This approach enables integration of multi-port RF components into large-signal and small-signal simulations, mirroring the capabilities of commercial design tools. The proposed API is fully modular, supporting multiple open-source PDKs, arbitrary passive networks, and various circuit configurations.
Congrats to Engin, and Gebze Technical University
RadiSPICE-L: A Layout-Centric Tool for Radiation-Aware Analog Circuit Design, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2025
Radiation effects pose a significant challenge in electronic circuits, impacting both reliability and performance. Prior simulation studies and tool developments have provided valuable insights into radiation effects at the circuit level, but further study requires including substrate effects. This paper proposes “RadiSPICE-L”, a layout-aware simulation tool developed in the Cadence environment using the SKILL language. The tool employs a resistor mesh network in order to simulate substrate interactions and incorporates a Gaussian-distributed current pulse network for precise modelling of Single Event Transients. Case studies including a bandgap reference circuit and a strong arm comparator confirm the effectiveness and the accuracy of RadiSPICE-L in identifying radiation-sensitive regions and evaluating layout-based charge mitigation strategies, such as guard rings, to enhance circuit robustness.
Congrats to Engin, and Gebze Technical University
Multi-Objective Optimization of Analog Circuits Using Reinforcement Learning, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2025
Analog circuit design requires balancing conflicting performance metrics, making an accurate Pareto-Optimal Front (PoF) essential for trade-off analysis. Meta-heuristic algorithms are commonly employed to explore the PoF; however, the computational complexity involved in PoF exploration and the tendency to converge on suboptimal designs remain significant challenges that have yet to be fully addressed. This work introduces Multi-Objective Deep Deterministic Policy Gradient (MODDPG) for efficient PoF extraction in analog circuit design. By combining Reinforcement Learning (RL) with multi-objective optimization, MODDPG navigates high-dimensional design spaces more effectively than the conventional methods. It leverages a continuous action space and a tailored reward function to iteratively refine the design parameters. To validate the performance of the proposed approach, several MOO benchmark problems have been successfully solved. Then, experiments on analog circuit benchmarks have been perfromed to demonstrate that MODDPG outperforms traditional methods in key metrics, notably maximizing the Figure of Merit (FoM) and significantly advancing automation in circuit optimization.
Congrats to Bo, and University of Glasgow, UK
An AI-driven EDA Algorithm-Empowered VCO and LDO Co-Design Method, 2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD)
Traditionally, the output noise and power supply rejection of low-dropout regulators (LDOs) are optimized to minimize power supply fluctuations, reducing their impact on the low-frequency noise of target voltage-controlled oscillators (VCOs). However, this sequential design approach does not fully address the trade-offs between high-frequency and LDO-induced low-frequency phase noise. To overcome this limitation, this paper presents a co-design method for low phase-noise LC-tank VCOs powered by LDOs. It is difficult to carry out the co-design using traditional manual design techniques. Hence, an efficient AI-driven EDA algorithm is used. To validate the proposed method, a 5.6 GHz LC-tank VCO with an integrated LDO is designed using a 65 nm CMOS process. Simulations show that the co-design method improves phase noise by 1.2 dB at a 1 MHz offset and reduces dynamic power consumption by 28.8%, with FoM increased by 2.4 dBc/Hz compared to the conventional sequential design method.
Congrats to Bo, and University of Glasgow, UK
Behavioral study of Bayesian neural networks under a typical surrogate model-assisted evolutionary search framework, IEEE ACCESS
Traditionally, the output noise and power supply rejection of low-dropout regulators (LDOs) are optimized to minimize power supply fluctuations, reducing their impact on the low-frequency noise of target voltage-controlled oscillators (VCOs). However, this sequential design approach does not fully address the trade-offs between high-frequency and LDO-induced low-frequency phase noise. To overcome this limitation, this paper presents a co-design method for low phase-noise LC-tank VCOs powered by LDOs. It is difficult to carry out the co-design using traditional manual design techniques. Hence, an efficient AI-driven EDA algorithm is used. To validate the proposed method, a 5.6 GHz LC-tank VCO with an integrated LDO is designed using a 65 nm CMOS process. Simulations show that the co-design method improves phase noise by 1.2 dB at a 1 MHz offset and reduces dynamic power consumption by 28.8%, with FoM increased by 2.4 dBc/Hz compared to the conventional sequential design method.