Our Know-How
The consortium brings together a multidisciplinary team with deep expertise in AI-powered circuit design, encompassing advanced methodologies in analog/RF design automation, machine learning, reinforcement learning and meta-modeling, supported by years of research and practical deployment across academic and industrial domains.
Fully Automatically Synthesized mm-Wave Low-Noise Amplifiers for 5G/6G Applications
Paper describing the first end-to-end synthesis optimization procedure for mm-Wave circuits in CMOS technologies. The methodology includes sizing and layout automatization in a complete integrated manner and without human intervention. L. Mendes, J. Silva, N. Lourenço, J. C. Vaz, R. Martins and F. Passos (2025). “Fully Automatically Synthesized mm-Wave Low-Noise Amplifiers for 5G/6G Applications,” in IEEE Transactions on Microwave Theory and Techniques.
An efficient and general automated power amplifier design method based on surrogate model assisted hybrid optimization technique
GASPAD series (I-II) addressing key bottlenecks in AI-driven RFIC design. e.g., GASPAD-II: Liu, Bo, et al. (2025) “An efficient and general automated power amplifier design method based on surrogate model assisted hybrid optimization technique.” IEEE Transactions on Microwave Theory and Techniques (in press), firstly realized high-performance wideband mm-wave IC design without good initial design. Partly due to this, a partnership is built with Cadence.
A multilevel bottom-up optimization methodology for the automated synthesis of RF systems
Passos, F., Roca, E., Sieiro, J., Fiorelli, R., Castro-López, R., López-Villegas, J. M., & Fernández, F.V., IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.39, no.3, pp. 560-571, 2019. OPENACCESS: http://hdl.handle.net/10261/205076
Ready-to-fabricate RF circuit synthesis using a layout-and variability-aware optimization-based methodology,
Passos, F., Roca, E., Martins, R., Lourenço, N., Ahyoune, S., Sieiro, J., Castro-López, R., Horta, N., Fernandez, F. V. IEEE Access, vol. 8, pp. 51601-51609, 2020. DOI: 10.1109/ACCESS.2020.2980211
Analysis of Back-Gate Bias Control on EVM Measurements of a Dual-Band Power Amplifier in 22 nm FD-SOI for 5G 28 and 39 GHz Applications
This paper highlights the impact of back-gate bias control on EVM performance as a key enabler for reconfigurable and AI-assisted mmWave power amplifier design in 22 nm FD-SOI for 5G 28 and 39 GHz bands. L. Nyssens, AU – L. Nyssens, M. Nabet, M. Rack, Y. Bendou, S. Wane, J. B. Sombrin, J.-P. Raskin and D. Lederer “,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 72, no. 2, pp. 753-762, Feb. 2025
Radio-frequency inductor synthesis using evolutionary computation and Gaussian-process surrogate modeling
F. Passos, E. Roca, R. Castro-López, F.V. Fernández, Applied Soft Computing, Vol. 60, pp. 495-507, 2017. https://doi.org/10.1016/j.asoc.2017.07.036. OPEN ACCESS: http://hdl.handle.net/10261/153730.
An efficient method for antenna design optimization based on evolutionary computation and machine learning techniques
SADEA series (I-VI) addresses key bottlenecks in AI-driven antenna design and is widely used in industry and academia. e.g., SADEA-I: Liu, Bo, et al. (2014) “An efficient method for antenna design optimization based on evolutionary computation and machine learning techniques.” IEEE transactions on antennas and propagation, is the first AI-driven antenna design technology practical for industry use. Due to this, a partnership is built with MathWorks and Ansys.
An efficient analog circuit sizing method based on machine learning-assisted global optimization
ESSAB series (I-II) addressing key bottlenecks in AI-driven analog IC design. e.g., ESSAB-I: Budak, A. F., …, Liu, B. (2021). An efficient analog circuit sizing method based on machine learning-assisted global optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(5), addresses the key bottleneck of long training time and hard-to-learn performance metrics. Partly due to this, a partnership is built with Cadence.
An unsupervised microwave filter design optimization method based on a hybrid surrogate model-assisted evolutionary algorithm.
SMEAFO series (I-II) is the first to realize the fully automated AI-driven design of microwave filters. The one-button approach allows average-level engineers to obtain high-performance filter designs. e.g., SMEAFO-II: Xue, L., Liu, B., et. al., (2022). An unsupervised microwave filter design optimization method based on a hybrid surrogate model-assisted evolutionary algorithm. IEEE Transactions on Microwave Theory and Techniques, 71(3).
PACOSYT: A Passive Component Synthesis Tool Based on Machine Learning and Tailored Modeling Strategies Towards Optimal RF and mm-Wave Circuit Designs
Paper describing the modeling, design and optimization of passive components. The tool can synthesize passives, as an end-to-end synthesis procedure for passive components. F. Passos et al, (2023). “PACOSYT: A Passive Component Synthesis Tool Based on Machine Learning and Tailored Modeling Strategies Towards Optimal RF and mm-Wave Circuit Designs,” In IEEE Journal of Microwaves, vol. 3, no. 2, pp. 599-613, April 2023.
Synthesis of mm-Wave Wideband Receivers in 28-nm CMOS Technology for Automotive Radar Applications
Paper describing the first bottom-up synthesis optimization procedure for mm-Wave circuits in CMOS technologies and applied in an industrial environment in collaboration with the company Analog Devices, one of the biggest companies in the semiconductor industry. F. Passos, M. Chanca, E. Roca, R. Castro-López and F. V. Fernández (2020). “Synthesis of mm-Wave Wideband Receivers in 28-nm CMOS Technology for Automotive Radar Applications,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 12, pp. 4375-4384, Dec. 2020.
An evolutionary approach to automatic synthesis of high-performance analog integrated circuits
One of the very first papers using evolutionary strategies to optimize analog integrated circuits. Has been cited more than 200 times according to google scholar, G. Alpaydin, S. Balkir, and G. Dündar, ” IEEE Trans. On Evolutionary Computation, Vol. 7, No. 3, pp. 240-252, 2003, doi: 10.1109/TEVC.2003.808914.
Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test
Probably the first survey paper in this field. Has received around 130 citations according to google scholar. E. Afacan, N. Lourenço, R. Martins, and G. Dündar, ” Integration, Vol. 77, pp. 113-130, 2021, doi: 10.1016/j.vlsi.2020.11.006. Invited survey paper about machine learning in analog IC design.
Artificial neural network assisted analog IC sizing tool
Using neural network modelling in circuit optimization. Has been cited more than 50 times according to google scholar. T. İslamoğlu, O.Ç. Çakıcı, E. Afacan, and G. Dündar, Proc. SMACD, 2019, doi: 10.1109/SMACD.2019.8795293.
On Chip Reconfigurable CMOS Analog Circuit Design and Automation Against Aging Phenomena: Sense and React
Self configuration of circuits against aging as in the proposed Project. E. Afacan, G. Dündar, F. Başkaya, A.E. Pusane, M.B. Yelten, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 24, No.4, pp. 1-22, 2019, doi: 10.1145/3325069.
Analog VLSI Design Automation
Book about the design automation of analog circuits from system level to circuit level and layout level and the associated interactions. One of the first books in this field at its time. S. Balkır, G. Dündar, A.S. Öğrenci, published by CRC Press, 2003, doi:10.1201/9780203492758.
A DC-120 GHz SPDT Switch Based on 22 nm FD-SOI SLVT NFETs with Substrate Isolation Rings Towards Increased Shunt Impedance
M. Rack, L. Nyssens, Q. Courte, D. Lederer and J.-P. Raskin, 2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2022, pp. 83-86.
A 2.5-2.6 dB Noise Figure LNA for 39 GHz band in 22 nm FD-SOI with Back-Gate Bias Tunability
L. Nyssens, M. Rack, S. Wane, C. Schwan, S. Lehmann, Z. Zhao, L. Lucci, J. Lugo-Alvarez, F. Gaillard, J.-P. Raskin and D. Lederer, 2022 17th European Microwave Integrated Circuits Conference (EuMIC), 2022, pp. 60-63.
SPST and SPDT 60 GHz Travelling-Wave Switches in 22 nm FD-SO
Q. Courte, M. Rack, D. Lederer and J. -P. Raskin, 2023 18th European Microwave Integrated Circuits Conference (EuMIC), Berlin, Germany, 2023, pp. 313-316.
A Compact 120 GHz LNA in 22 nm FD-SOI with Back-Gate Controllable Variable-Gain
M. Rack, L. Nyssens, Q. H. Le, D. K. Huynh, T. Kämpfe, J.-P. Raskin, and D. Lederer, 2023 18th European Microwave Integrated Circuits Conference (EuMIC), Berlin, Germany, 2023, pp. 386-389
Sub-mmWave Transmission Lines on Silicon-Based Technologies
S. Ma, L. Nyssens, J. -P. Raskin and D. Lederer, 2023 53rd European Microwave Conference (EuMC), Berlin, Germany, 2023, pp. 42-45.
